Integrated circuit microprocessors must, in many cases, be connected with other integrated circuit devices in order to provide certain functions. Examples of such external devices include memories, serial interface adaptors, analog-to-digital converters and many others. In most cases, each such external device will require external control signals in order for the device to be appropriately activated when accessed by the microprocessor. For example, a static random access memory (SRAM) integrated circuit requires the chip enable, output enable, and write enable control signals to control read and write accesses. The timing requirements of these signals differ somewhat between commercially available devices. For example, some SRAMs provide output data asynchronously with respect to the output enable signal, whereas other SRAMs sample output enable and provide output data synchronously with a clock signal.
Typically, a designer of a system using a microprocessor and other integrated circuits will use "glue logic" to generate the required chip select signals from the address and bus control signals produced by the microprocessor itself. This extra logic adds significantly to the cost of the system being designed and may degrade performance, and therefore is highly undesirable.
The 80186 (also referred to as the iAPX 186), available from the Intel Corporation of Santa Clara, California, is an integrated circuit microprocessor which has internal logic for generating chip select signals. The chip select logic has limited ability to program the address range for which each of the seven possible chip selects is active and can programmably insert wait states into the bus cycles for which each chip select is active. In addition, some of the chip selects may be programmed to be active in only the memory or I/O address spaces of the microprocessor.
Another example of an integrated circuit microprocessor with on-board chip select logic is that disclosed by John A. Langan and James M. Sibigtroth in U.S. Pat. No. 5,151,986, issued Sep. 29, 1992. The disclosed chip select logic includes a control register by means of which the timing, polarity and number of wait states can be individually programmed for each of several chip select outputs.
A major problem associated with the integration of chip select logic onto a microprocessor integrated circuit involves the provision of sufficient flexibility to the user. The use of glue logic is extremely flexible, since the system designer has wide latitude in the placement of each external device with the microprocessor's memory map and the timing and other characteristics of the chip select signals themselves. This flexibility is very useful, since the variety of possible system designs and chip select requirements for particular peripheral devices is great. Providing sufficient flexibility in an integrated chip select unit while constraining the size of the unit within reasonable limits is quite difficult.
One type of flexibility is the ability to support CPUs with burst mode capability. Burst mode is a mode in which the CPU accesses a series of memory locations in consecutive clock cycles. For example, the CPU may read several words of data from memory as part of a move instruction by reading the words in consecutive clock cycles. Commercially available high-speed SRAMs support burst mode through a feature known as page mode, nibble mode, static column, or the like. However, these SRAMs require cores with short access time in order to provide the data within one clock cycle, and thus are generally expensive.